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FPGA Events at SC 2005
SC05 BOF-22: Programming standards for FPGAs in HPC Applications Organizers and Presenters: Note: The following is an approximate transcript of the presentation and discussion at the BOF. The content was generated from accumulated notes and not from a recorded dictation. Errors in content may be present. OpenFPGA is targeted at a diverse audience. It includes this comfortable with FPGAs and those comfortable with HPC. This is the time to bring everyone together. Goal is to become official in 1Q 2006. Who is it targeted at? After the presentation, if you want to get involved -- signup at the website, get involved in working groups, get on the mailing list to monitor. Discussion of what an FPGA is. Why the interest in FPGAs now? FPGAs have been around in the role of glue logic. In that manner, very much akin to the microprocessor, with early versions used as simple controllers. Now for FPGAs, there are incredible increases of speeds and densities. Floating point becoming viable and cost is going down. Along with that, years of work on design tools. Algorithms to implementation tools have been improving at an immense rate. Good stuff. But if performance isn't there, it doesn't matter. Do FPGAs provide a motivation for a paradigm shift? GE spends a lot of resources on CFD problems -- e.g. blade on a turbine. Here's a graph that shows a profile of the internal codes. This represents about 85% of HPC utilization at GE. Highlighted Smoother, Euler, Viscous taking about 50% of total together. Hours of time in the conventional computer are required. Eliminate the run-time for the section and great run times can be achieved. Why does the FPGA have potential? If the speed-up was just one application -- it would be exciting to a subset of attendees. But research on the web showed areas where FPGAs are employed: Seismic, Genomic, Encryption, and N-body simulation. In fact, n-body simulations are on the floor. Is the FPGA faster today? What about the future? FPGA is targeted to be order of magnitude ahead of general purpose CPUs in a short amount of time. General limitations are bandwidth, does the FPGA have the upper-hand? Great FPGA is the way to boost performance. Still, how do I program the FPGA? What has to be done additionally to use an FPGA? Take the Euler code example. It took 7 months for this process to get to FPGA level. Not acceptable, given that 1 month is the window within which demonstrable results are required. Thankfully, smart people building tools to capture this and bring it down to hardware. At best, it takes software specification and to do a port. HLL Roundup -- Partial list of vendors, each has different underlying assumptions about the hardware. Not exhaustive list. If there are people aware of other efforts, get on the OpenFPGA website. If you are interested in these, many of the vendors are in the audience or on the floor. But there are still problems. Projects diverge into multiple code bases. Have tools, but still have problems. How are these going to mature? What is keeping FPGAs from going mainstream? <Turn over to Malachy Devlin> Applications you can do many great things. Still it tends to be in research community. What is required to take mainstream? Sam Allisant from IBM -- one of the factors keeping it from going Whose primary funding force between OpenFPGA organization? OSC gracious to donate effort to start it. It's a grass roots organization. Comment: We are looking to take it to the next stage. How do these languages compare to Verilog? Verilog is an HDL. System Verilog and VHDL type tools. MAPLD had a list of things to standardize. Obvious thing is to have the same API for things to make easier C-calls. On the FPGA-end a standard interface for FIFOs. Every interconnect will be different, but if there was a standard FIFO to hide differences between vendors. Need to come up with a thorough list of what these are. Wondering if there was a difference in clock-rate and density for 5 week design relative to 7 month effort? From the company's perspective, what are things to do to sell it inside? Goal is to get things into the hands of the domain experts. Get FORTRAN guy to be able to redo what he does. Also a lack of hardware inhibits internal use. Two things would help a lot. Standardize language across platforms. This is becoming less and less of an issue. Handle-C, VIVA, Mitrion Impulse-C are supporting multiple hardware. Another thing that might help, enable targets to non-optimal code for simulation on GP CPU. So basically there are two sides: user side and vendor side. Vendors want to differentiate and special functions to port to memory. Users have two Comes from hardware background, the motivation to tune is strong with a hardware person. I have to say impressed with HLL results in past couple of years. Think of being very similar to HLL and assembly language. Past problems include the need to pay $100,000 for specific equipment, want to use vendor specific capabilities. Arguments are similar to the MPI arguments. Vendors were very concerned about their own sends and receives. But have to realize that MPI is successful, if because we did agree on a standard. So programs can be written. If you can get to at least basic sets, then C extension, C-API then a lot will be gained. May not be satisfactory with everyone. MPI was funded with NSF with university and vendor support. Don't define yourself away. MPI was defined to be POSIX aware. Rusty Lusk from Argonne made sure MPI was to be thread aware. Most applications outlive the hardware. If one is going to invest in an accelerator, what are the options when the accelerator is obsolete. It's a very real issue. MPI has allowed apps to move on to new hardware. Need to emulate that type of transparency. There is an analogy with FPGAs. Can't port until it can be compiled. Kevin from FPGA Journal. Need to have three components to get application developed. Here people getting confused. Start with procedural language. Only way is to have cake and eat it too. First is a HLL with no hardware at all. A second language which is application specific. If it's within code, then it's hard to scale up to new hardware. GE has huge pieces of code that would be good to move. Problem is loss of original developers. In the next piece of this, talk about standards. A caution. Is the problem compute bound or I/O bound? Audio processing, for example. It may be possible to allow creating virtual machine specific with the instructions. Create a "super operator" The whole idea in VM space is great. A company called AZOUL [?] looking to add primitives with virtual machines. FPGAs are a means to an end. What about and SRAM in core? Seems FPGAs are clunky and big. Actually example have taken FPGA fabric and put in the instruction path. Talked about CFD code, but also FPGAs are used for advanced CT reconstruction. In this situation, we had to create very different architecture. Maybe question, are there examples of domain specific processors? Want to be more productive. Go to the other extreme. Thousands of lines of code for the HLL. The question for the FPGAs, new models comes back to standards. What bits to standardize, what's the order? Maya listed several of them and are a good start. Has anyone else had frustrations which would be better suited to standards? Hard enough to learn one thing. David Peller -- standardized interfaces for toolflows that can work together. Just like OS layering. Get the interconnect well defined. Some standardized specification that various tools can write to. Hearing standards for FPGA? What about higher level standards? GMU and GW University -- trying to create a standard set of tools to deploy across platforms. Challenging when approaches are very different and different pins are blocked off. Need to define some pins accepted by vendors, partial reconfiguration, etc. Dicey call, a specific processor but generic enough to be portable. Absolutely right. All agree that FPGAs and processors will sit side by side. At EPCC -- don't want to learn VHDL. Dave Pointer -- NCSA -- hearing a lot of vendors giving us what we want. Discussion continued with review of the working groups forming |